description the a3966 is designed to drive both windings of a two-phase bipolar stepper motor. the device includes two full-bridges capable of continuous output currents of 650 ma and operating voltages to 30 v. motor winding current can be controlled by the internal fixed-frequency, pulse-width modulated (pwm), current-control circuitry. the peak load current limit is set by user selection of a reference voltage and current-sensing resistors. the fixed-frequency pulse duration is set by a user-selected external rc timing network. the capacitor in the rc timing network also determines a user-selectable blanking window that prevents false triggering of the pwm current-control circuitry during switching transitions. to reduce on-chip power dissipation, the full-bridge power outputs have been optimized for low saturation voltages. the sink drivers feature the allegro ? patented satlington ? output structure. the satlington outputs combine the low voltage drop of a saturated transistor and the high peak current capability of a darlington. for each bridge, a phase input controls load-current polarity by selecting the appropriate source and sink driver pair. for 29319.25k features and benefits ? 650 ma continuous output current ? 30 v output voltage rating ? internal fixed-frequency pwm current control ? satlington? sink drivers ? user-selectable blanking window ? internal ground-clamp and flyback diodes ? internal thermal-shutdown circuitry ? crossover-current protection and uvlo protection dual full-bridge pwm motor driver continued on the next page? package: 16 pin soicw (suffix lb) typical application not to scale a3966 dwg. ep-047-4a phase 2 enable 2 47 f + +24 v 56 k 680 pf phase 1 enable 1 +5 v 39 k 10 k 0.5 +5 v 0.5 logic logic 1 2 3 14 15 16 6 0 1 7 11 9 8 rc 4 5 v ref 13 12 v bb v cc v bb
dual full-bridge pwm motor driver a3966 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com each bridge, an enable input, when held high, disables the output drivers. special power-up sequencing is not required. internal circuit protection includes thermal shutdown with hysteresis, ground-clamp and flyback diodes, and crossover-current protection. the a3966 is supplied in a 16-lead plastic wide soic with two pins internally fused to the die pad for enhanced thermal dissipation. these pins are at ground potential and need no electrical isolation. the device is lead (pb) free, with 100% matte tin leadframe plating. description (continued) pin-out diagram selection guide part number packing ambient temperature range (c) A3966SLBTR?t 1000 pieces / reel ?20 to 85 absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 30 v logic supply voltage v cc 7.0 v input voltage v in ?0.3 to v cc + 0.3 v sense voltage v s 1.0 v output current* i out peak output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or t j (max) 750 ma continuous 650 ma package power dissipation p d t a = 25c; per semi g42-88 specification, thermal test board standardization for measuring junction-to-ambient thermal resistance of semiconductor packages. 1.87 w operating ambient temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc out 1b ground ground out 1a phase 1 out 2a sense 1 enable 1 load supply reference phase 2 enable 2 sense 2 out 2b logic supply rc logic logic 1 2 3 14 15 16 6 0 1 7 11 9 8 rc 4 5 v ref 13 12 v bb v cc v bb
dual full-bridge pwm motor driver a3966 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram truth table phase enable out a out b x h off off h l h l l l l h x = irrelevant r 2s r 1s reference 4 v cc logic supply phase 1 load supply out 1a out 1b v bb rc r t c t dwg. fp-036-6 sense uvlo & tsd blanking gate q r s pwm latch + ? current-sense comparator enable 1 osc + phase 2 ground sense uvlo & tsd blanking gate q r s pwm latch + ? current-sense comparator enable 2 control logic source enable out 2a out 2b 2 1 2 2 2 2 2 1 1 1 control logic 1 source enable 1 typical output saturation voltages showing satlington sink-driver operation. 200 dwg. gp-064-1a 0 0 7 0 0 4 300 output current in milliamperes 2.0 output saturation voltage in volts 1.0 0 0.5 1.5 2.5 500 600 t a = +25 c source driver sink driver
dual full-bridge pwm motor driver a3966 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com load supply voltage range v bb operating, i out = p 650 ma, l = 3 mh v cc ?30 v output leakage current i cex v out 0 5 0 . 1 < ? v 0 3 = m a v out 0 5 - 0 . 1 - < ? v 0 = m a output saturation voltage v ce(sat) source driver, i out = -400 ma ? 1.7 2.0 v source driver, i out = -650 ma ? 1.8 2.1 v sink driver, i out = +400 ma, v s = 0.5 v ? 0.3 0.5 v sink driver, i out = +650 ma, v s = 0.5 v ? 0.7 1.3 v clamp diode forward voltage v f i f v 4 . 1 1 . 1 ? a m 0 0 4 = i f v 6 . 1 4 . 1 ? a m 0 5 6 = motor supply current i bb(on) v enable1 = v enable2 = 0.8 v ? 3.0 5.0 ma (no load) i bb(off) v enable1 = v enable2 = 2.4 v ? <1.0 200 m a electrical characteristics at t a = +25 o c, v bb = 30 v, v cc = 4.75 v to 5.5 v, v ref = 2 v, v s = 0 v, 56 k ? & 680 pf rc to ground (unless noted otherwise) limits s t i n u . x a m . p y t . n i m s n o i t i d n o c t s e t l o b m y s c i t s i r e t c a r a h c output drivers logic supply voltage range v cc v 0 5 . 5 ? 5 7 . 4 g n i t a r e p o logic input voltage v in(1) 2.4 ? ? v v in(0) ? ? 0.8 v logic input current i in(1) v in 0 2 0 . 1 < ? v 4 . 2 = m a i in(0) v in 0 0 2 - 0 2 - < ? v 8 . 0 = m a reference input volt. range v ref v 0 . 2 ? 1 . 0 g n i t a r e p o reference input current i ref -2.5 0 1.0 m a reference divider ratio v ref /v trip 3.8 4.0 4.2 ? current-sense comparator v io v ref v m 0 . 6 0 0 . 6 - v 0 = input offset voltage current-sense comparator v s v 0 . 1 ? 3 . 0 - g n i t a r e p o input voltage range sense-current offset i so i s ?i out , 50 ma b i out b 650 ma 12 18 24 ma control logic notes:1. typical data is for design information only. 2. negative current is defined as coming out of (sourcing) the specified device terminal.
dual full-bridge pwm motor driver a3966 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pwm rc frequency f osc c t = 680 pf, r t = 56 k 7 22.9 25.4 27.9 khz pwm propagation delay time t pwm comparator trip to source off ? 1.0 1.4 m s cycle reset to source on ? 0.8 1.2 m s cross-over dead time t codt 1k ? 0 . 3 8 . 1 2 . 0 v 5 2 o t d a o l m s propagation delay times t pd i out = p 650 ma, 50% to 90%: enable on to source on ? 100 ? ns enable off to source off ? 500 ? ns enable on to sink on ? 200 ? ns enable off to sink off ? 200 ? ns phase change to sink on ? 2200 ? ns phase change to sink off ? 200 ? ns phase change to source on ? 2200 ? ns phase change to source off ? 200 ? ns thermal shutdown temp. t j ?165? o c thermal shutdown hysteresis $ t j ?15? o c uvlo enable threshold v t(uvlo)+ increasing v cc ? 4.1 4.6 v uvlo hysteresis v t(uvlo)hys 0.1 0.6 ? v logic supply current i cc(on) v enable 1 = v enable 2 = 0.8 v ? ? 50 ma i cc(off) v enable 1 = v enable 2 = 2.4 v ? ? 9.0 ma limits s t i n u . x a m . p y t . n i m s n o i t i d n o c t s e t l o b m y s c i t s i r e t c a r a h c electrical characteristics at t a = +25 o c, v bb = 30 v, v cc = 4.75 v to 5.5 v, v ref = 2 v, v s = 0 v, 56 k ? & 680 pf rc to ground (unless noted otherwise) (cont.) control logic (continued) notes:1. typical data is for design information only. 2. negative current is defined as coming out of (sourcing) the specified device terminal.
dual full-bridge pwm motor driver a3966 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com internal pwm current control. the a3966 dual full- bridges are designed to drive both windings of a bipolar stepper motor. load current can be controlled in each motor winding by an internal xed-frequency pwm control cir- cuit. the current-control circuitry works as follows: when the outputs of the full-bridge are turned on, current increas- es in the motor winding. the load current is sensed by the current-control comparator via an external sense resistor (r s ). load current continues to increase until it reaches the predetermined value, set by the selection of external current-sensing resistors and reference input voltage (v ref ) according to the equation: i trip = i out + i so = v ref /(4 r s ) where i so is the sense-current error (typically 18 ma) due to the base-drive current of the sink driver transistor. at the trip point, the comparator resets the source-en- able latch, turning off the source driver of that full-bridge. the source turn-off of one full-bridge is independent of the other full-bridge. load inductance causes the current to recirculate through the sink driver and ground-clamp diode. the current decreases until the internal clock oscillator sets the source-enable latches of both full-bridges, turning on the source drivers of both bridges. load current increases again, and the cycle is repeated. the frequency of the internal clock oscillator is set by the external timing components r t c t . the frequency can be approximately calculated as: f osc = 1/(r t c t + t blank ) where t blank is de ned below. the range of recommended values for r t and c t are 20 to 100 k ? and 470 to 1000 pf respectively. nominal values of 56 k ? and 680 pf result in a clock frequency of 25 khz. current-sense comparator blanking. when the source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switch- ing transients related to distributed capacitance in the load. to prevent this current spike from erroneously resetting the source enable latch, the current-control comparator output is blanked for a short period of time when the source driver is turned on. the blanking time is set by the timing compo- nent c t according to the equation: t blank = 1900 c t ( s). a nominal c t value of 680 pf will give a blanking time of 1.3 s. the current-control comparator is also blanked when the full-bridge outputs are switched by the phase or enable inputs. this internally generated blank time is approximately 1 s. functional description + ? 0 dwg. wm-003-2 v phase i out t d i trip t blank internal oscillator bridge on source off bridge on r c t t all off enlargement a see enlargement a dwg. ep-006-16 r s bb v bridge on source off all off
dual full-bridge pwm motor driver a3966 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com load current regulation. due to internal logic and switching delays, t d , the actual load current peak will be slightly higher than the i trip value. these delays, plus the blanking time, limit the minimum value the current control circuitry can regulate. to produce zero current in a wind- ing, the enable terminal should be held high, turning off all output drivers for that full-bridge. logic inputs . a logic high on the phase input results in current owing from out a to out b of that full-bridge. a logic low on the phase input results in current owing from out b to out a . an internally generated dead time, t codt , of approximately 1 s prevents crossover-current spikes that can occur when switching the phase input. a logic high on the enable input turns off all four output drivers of that full-bridge. this results in a fast cur- rent decay through the internal ground clamp and yback diodes. a logic low on the enable input turns on the selected source and sink driver of that full-bridge. the enable inputs can be pulse-width modulated for applications that require a fast current-decay pwm. if external current-sensing circuitry is used, the internal cur- rent-control logic can be disabled by connecting the r t c t terminal to ground. the reference input voltage is typically set with a resistor divider from v cc . this reference voltage is inter- nally divided down by 4 to set up the current-comparator trip-voltage threshold. the reference input voltage range is 0 to 2 v. output drivers . to minimize on-chip power dissipa- tion, the sink drivers incorporate a satlington structure. the satlington output combines the low v ce(sat) features of a saturated transistor and the high peak-current capabil- ity of a darlington (connected) transistor. a graph showing typical output saturation voltages as a function of output current is on page 5. miscellaneous information . thermal protection circuitry turns off all output drivers should the junction temperature reach 165 c typical. this is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. normal operation is resumed when the junc- tion temperature has decreased about 15c. the a3966 current control employs a xed-frequency, variable duty cycle pwm technique. as a result, the cur- rent-control regulation may become unstable if the duty cycle exceeds 50%. to minimize current-sensing inaccuracies caused by ground trace i r drops, each current-sensing resistor should have a separate return to the ground terminal of the device. for low-value sense resistors, the i x r drops in the printed- wiring board can be signi cant and should be taken into ac- count. the use of sockets should be avoided as their contact resistance can cause variations in the effective value of r s . the load supply terminal, v bb , should be decou- pled with an electrolytic capacitor (47 f recommended) placed as close to the device as physically practical. to minimize the effect of system ground i x r drops on the logic and reference input signals, the system ground should have a low-resistance return to the load supply voltage. the frequency of the clock oscillator will determine the amount of ripple current. a lower frequency will result in higher current ripple, but reduced heating in the motor and driver ic due to a corresponding decrease in hysteretic core losses and switching losses respectively. a higher frequen- cy will reduce ripple current, but will increase switching losses and emi. functional description (continued)
dual full-bridge pwm motor driver a3966 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lb, 16-pin soicw copyright ?1998-2013, allegro microsystems, llc satlington? is a registered trademark of allegro microsystems, llc (allegro), and satlington devices are manufactured under u . s. patent no. 5,684,427. allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com 9.50 0.65 2.25 1.27 c seating plane c 0.10 16x 1.27 0.25 0.20 0.10 0.41 0.10 2.65 max 10.300.33 7.500.10 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 10.300.20 2 1 16 gauge plane seating plane for reference only pins 4 and 13 fused internally dimensions in millimeters (reference jedec ms-013 aa) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area a b reference pad layout (reference ipc soic127p1030x265-16m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b pcb layout reference view
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